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1 x9241a quad digital controlled potentionmeters (xdcp?) non-volatile/low power/2-wire/64 taps the x9241a integrates four digitally controlled potentiometers (xdcp) on a m onolithic cmos integrated microcircuit. the digitally controlled potent iometer is implemented using 63 resistive elements in a s eries array. between each element are tap points connected to the wiper terminal through switches. the position of the wiper on the array is controlled by the user through t he 2-wire bus interface. each potentiometer has associated with it a volatile wiper counter register (wcr) and 4 nonvo latile data registers (dr0:dr3) that can be directly written to and read by the user. the contents of the wcr controls the position of the wiper on the resistor array through the switches. power up recalls the contents of dr0 to the wcr. the xdcp can be used as a three-terminal potentiometer or as a two-terminal va riable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. features ? four potentiomete rs in one package ? 2-wire serial interface ? register oriented format - direct read/write/transfe r of wiper positions - store as many as four pos itions per potentiometer ? terminal voltages: +5v, -3.0v ? cascade resistor arrays ? low power cmos ? high reliability - enduranceC100,000 data c hanges per bit per register - register data retentionC100 years ? 16-bytes of nonvolatile memory ? 3 resistor array values -2k ??? 10k ??? 50k ?? or combination - cascadable for values of 4k ?? to 200k ? ? resolution: 64 taps each pot ? 20 ld plastic dip, 20 l d tssop and 20 ld soic packages ? pb-free available (rohs compliant) block diagram data 8 r1 r0 r3 r2 v h0 /r h0 v l0 /r l0 v w0 /r w0 wiper counter register (wcr) v h1 /r h1 v l1 /r l1 v w1 /r w1 register array pot 1 wiper counter register (wcr) r1 r0 r3 r2 scl sda a0 a1 a2 a3 interface and control circuitry v h2 / v l2 /r l2 v w2 /r w2 v h3 /r h3 v l3 /r l3 v w3 /r w3 register array pot 2 wiper counter register (wcr) r1 r0 r3 r2 register array pot 3 wiper counter register (wcr) r1 r0 r3 r2 v cc v ss r h2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2005, 2006, 2007, 2015. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
2 fn8164.7 august 17, 2015 ordering information part number part marking v cc limits (v) potentiometer organization (k) temp range (c) package (rohs compliant) x9241ampz (note) (no longer available, recommended replacement: x9241amszt1) x9241ampz 5 10% 2/10/50 pot 0 = 2k pot 1 = 10k pot 2 = 10k pot 3 = 50k 0 to +70 20 ld pdip*** x9241ampiz (note) (no longer available, recommended replacement: x9241amszt1) x9241ampiz -40 to +85 20 ld pdip*** x9241amsz* (note) x9241ams z 0 to +70 20 ld soic x9241amsiz* (note) x9241amsi z -40 to +85 20 ld soic x9241amvz (note) x9241am vz 0 to +70 20 ld tssop x9241amviz* (note) x9241am viz -40 to +85 20 ld tssop x9241awpiz (note) x9241awpiz 10 pot 0 = 10k pot 1 = 10k pot 2 = 10k pot 3 = 10k 0 to +70 20 ld pdip x9241awsz* (note) x9241aws z 0 to +70 20 ld soic x9241awsiz* (note) x9241awsi z -40 to +85 20 ld soic x9241awvz* (note) x9241aw vz 0 to +70 20 ld tssop x9241awviz* (note) x9241aw viz -40 to +85 20 ld tssop x9241aypz (note) (no longer available, recommended replacement: X9241AYSIZ) x9241aypz 2 pot 0 = 2k pot 1 = 2k pot 2 = 2k pot 3 = 2k 0 to +70 20 ld pdip*** x9241aysz* (note) x9241ays z 0 to +70 20 ld soic X9241AYSIZ* (note) x9241aysi z -40 to +85 20 ld soic x9241ayvz (note) (no longer available, recommended replacement: x9241ayviz) x9241ay vz 0 to +70 20 ld tssop x9241ayviz* (note) x9241ay viz -40 to +85 20 ld tssop x9241aupz (note) x9241aupz 5 10% 50 pot 0 = 50k pot 1 = 50k pot 2 = 50k pot 3 = 50k 0 to +70 20 ld pdip*** x9241aupiz (note) x9241aupiz -40 to +85 20 ld pdip*** x9241ausz* (note) x9241aus z 0 to +70 20 ld soic x9241ausiz* (note) x9241ausi z -40 to +85 20 ld soic x9241auvz* (note) (no longer available, recommended replacement: x9241auszt1) x9241au vz 0 to +70 20 ld tssop x9241auviz* (note) x9241au viz -40 to +85 20 ld tssop *add "t1" suffix for tape and reel. ***pb-free pdips can be used for through hole wave solder proce ssing only. they are not intended for use in reflow solder proc essing applications. note: these intersil pb-free pl astic packaged products employ sp ecial pb-free material sets; molding compounds/die attach mater ials and 100% matte tin plate plus anneal - e3 termination finish, which is r ohs compliant and compatible with both snpb and pb-free solderi ng operations. intersil pb-free products are msl classified at pb-free peak re flow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. x9241a
3 fn8164.7 august 17, 2015 pin descriptions host interface pins serial clock (scl) the scl input is used to clo ck data into and out of the x9241a. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open d rain output and may be wire- ored with any numbe r of open drain or open collector outputs. an open drain output r equires the use of a pull-up resistor. for selecti ng typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. address the address inputs are used to set the least significant 4-bits of the 8-bit slave a ddress. a match in the slave address serial data stream mus t be made with the address input in order to initiate c ommunication with the x9241a. potentiometer pins v h /r h (v h0 /r h0 to v h3 /r h3 ), v l /r l (v l0 /r l0 to v l3 /r l3 ) the r h and r l inputs are equivalent to the terminal connections on eith er end of a mechanical potentiometer. v w /r w (v w0 /r w0 to v w3 /r w3 ) the wiper outputs are equival ent to the wiper output of a mechanical potentiometer. pinout x9241a (20 ld dip, soic, tssop) top view principles of operation the x9241a is a highly integrat ed microcircuit incorporating four resistor arrays, their asso ciated registers and counters and the serial interface logic providing direct communication between the host and t he xdcp potent iometers. serial interface the x9241a supports a bidirecti onal bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the tr ansfer is a master and the device being controlled is the slave. the master will always initiate data transfers and pro vide the clock for both transmit and receive operations. therefore, the x9241a will be considered a slave devic e in all applications. clock and data conventions data states on the sda lin e can change onl y during scl low periods (t low ). sda state changes during scl high are reserved for indicating start and stop conditions. start condition all commands to the x9241a are preceded by the start condition, which is a high to l ow transition of sda while scl is high (t high ). the x9241a continuously monitors the sda and scl lines for the st art conditi on and will not respond to any command unt il this condition is met. stop condition all communications must be termi nated by a stop condition, which is a low to high transition of sda while scl is high. acknowledge acknowledge is a software c onvention used t o provide a positive handshake between the master and slave devices on the bus to indicate the succ essful receipt of data. the transmitting device, either t he master or the slave, will release the sda bus after tran smitting 8-bits. the master generates a ninth c lock cycle and durin g this period the receiver pulls the sda line low to acknowledge that it successfully received the 8- bits of data. see figure 7. the x9241a will respond wit h an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. if the command is followed by a data byte the x9241a will respond with a final acknowledge. pin names symbol description scl serial clock sda serial data a0 to a3 address v w0 /r w0 a0 a2 v h1 /r h1 sda v ss 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v cc a1 a3 scl x9241a v l0 /r l0 v h0 /r h0 v w1 /r w1 v l1 /r l1 v w3 /r w3 v l3 /r l3 v h3 /r h3 v w2 /r w2 v l2 /r l2 v h2 /r h2 v h0 /r h0 to v h3 /r h3 , v l0 /r l0 to v l3 /r l3 potentiometer pins (terminal equivalent) v w0 /r w0 to v w3 /r w3 potentiometer pins (wiper equivalent) pin names symbol description x9241a
4 fn8164.7 august 17, 2015 array description the x9241a is comprised of four resistor arrays. each array contains 63 discrete resistive segments that are connected in series. the physical ends o f each array are equivalent to the fixed terminals of a m echanical potentiometer (v h /r h and v l /r l inputs). at both ends of each array and between each resistor segment is a fet switch c onnected to the wiper (v w /r w ) output. within each individual array only one switch may be turned on at a time. these switches are controlled by the wiper counter register (wcr). the 6 least significant bits of the wcr are decoded to select, and enable, 1 of 64 switches. the wcr may be written direc tly, or it can be changed by transferring the c ontents of one of four associated data registers into the wcr. these data registers and the wcr can be read and writt en by the host system. device addressing following a start condition the master must output the address of the slave it is acc essing. the most significant 4-bits of the slave address are the device type identifier (refer to figure 1). for the x 9241a, this is fixed as 0101[b]. the next 4-bits of the slave address are the device address. the physical device address is defined by the state of the a0 to a3 inputs. the x9241a compa res the serial data stream with the address input state; a successf ul compare of all 4 address bits is required for t he x9241a to respond with an acknowledge. acknowledge polling the disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical 5ms eeprom write cycle time. once the stop condition is issued to indicate the end of the nonvolatile write command, the x9241a initiates the internal write cycle. ack polling can be initiated immediately. thi s involves issuing the start condition followed by the device slave address. if the x9241a is still busy with the wr ite operation, no ack will be returned. if the x9241a has co mpleted the wr ite operation, an ack will be returned and the master can then proceed with the next operation. flow 1. ack polling sequence instruction structure the next byte sent to the x9241a contains the instruction and register pointer information. the 4 most significant bits are the instruction. the next 4- bits point to one of four pots and when applicable they point to one of four associated registers. the format is in figure 2. the 4 high order bits define the instruction. the next 2-bits (p1 and p0) select which one of the four potentiometers is to be affected by the in struction. the last 2-bits (r1 and r0) select one of the four registe rs that are to be acted upon when a register oriented instruction is issued. four of the nine instructions end with the transmission of the instruction byte. the basic sequence is illustrated in figure 3 . these two-byte instructions exchange data between the wcr and one of the data registers. a tr ansfer from a data register to a wcr is essentially a write to a static ram. the response 1 0 0 a3 a2 a1 a0 device type identifier device address 1 figure 1. slave address nonvolatile write command completed enter ack polling issue start issue slave address ack returned? further operation? issue instruction proceed issue stop no yes yes proceed issue stop no i1 i2 i3 i0 p1 p0 r1 r0 potentiometer select register select instructions figure 2. instruction byte format x9241a
5 fn8164.7 august 17, 2015 of the wiper to this action will be delayed t stpwv . a transfer from wcr current wiper position to a data register is a write to nonvolatile memory and takes a minimum of t wr to complete. the transfer can occur between one of the four potentiometers and one of its ass ociated registers; or it may occur globally, wherein the transfer occurs between all four of the potentiometers and one of their associated registers. four instructions require a thre e-byte sequence to complete. these instructions transfer d ata between the host and the x9241a; either bet ween the host and one of the data registers or directly between the host and the wcr. these instructions are: read wcr, re ad the current w iper position of the selected pot; write wcr, change current wiper position of the select ed pot; read data register, read the contents of the selected nonvol atile register; write data register, write a new value to the selected data register. the sequence of o perations is shown in figure 4. the increment/decrement command is different from the other commands. once the command is issued and the x9241a has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fin e tuning capability to the host. for each scl clock pulse (t high ) while sda is high, the selected wiper will move one re sistor segment towards the v h /r h terminal. similarly, for ea ch scl clock pulse while sda is low, the selected wip er will move one resistor segment towards the v l /r l terminal. a detailed illustration of the sequence and timing for this operation is shown in figures 5 and 6 respectively. s t a r t 0101a3a2a1a0 a i3 i2 i1 i0 p1 p0 r1 r0 scl sda s t o p c k a c k figure 3. two-byte instruction sequence s t a r t 0 1 0 1 a3 a2 a1 a0 a i3 i2 i1 i0 p1 p0 r1 r0 scl sda s t o p cm dw d5 d4 d3 d2 d1 d0 c k a c k a c k figure 4. three-byte instruction sequence s t a r t 0 1 0 1 a3a2a1a0 i3 i2 i1 i0 p1 p0 r1 r0 scl sda s t o p x x i n c 1 i n c 2 i n c n d e c 1 d e c n a c k a c k figure 5. increment/decrement instruction sequence x9241a
6 fn8164.7 august 17, 2015 notes: 1. 1/0 = data is one or zero 2. x = not applicable or dont car e; that is, a data register is not involved in the operation and need not be addressed (typic al). scl sda v w /r w inc/dec cmd issued voltage out t clwv figure 6. increment/decrement timing limits table 1. instruction set instruction instruction format operation i 3 i 2 i 1 i 0 p 1 p 0 r 1 r 0 read wcr 1 0 0 1 1/0 (note 1) 1/0 x (note 2) x read the contents of the wiper counter register pointed to by p 1 to p 0 write wcr 1 0 1 0 1/0 1/0 x x write new value to the wiper counter regis ter pointed to by p 1 to p 0 read data register 1 0 1 1 1/0 1/0 1/0 1/0 read the contents of the register pointed to by p 1 to p 0 and r 1 to r 0 write data register 1 1 0 0 1/0 1/0 1/0 1/0 write new value to the register pointed to by p 1 to p 0 and r 1 to r 0 xfr data register to wcr 1 1 0 1 1/0 1/0 1/0 1/0 transfer the contents of the register pointed t o by p 1 to p 0 and r 1 to r 0 to its associated wcr xfr wcr to data register 1 1 1 0 1/0 1/0 1/0 1/0 transfer the contents of the wcr pointed to by p 1 to p 0 to the register pointed to by r 1 to r 0 global xfr data register to wcr 0 0 0 1 x x 1/0 1/0 transfer the contents of the data registers pointed to by r 1 to r 0 of all four pots to their respective wcr global xfr wcr to data register 1 0 0 0 x x 1/0 1/0 transfer the contents of all wcrs to their respecti ve data registers pointed to by r 1 to r 0 of all four pots increment/ decrement wiper 0 0 1 0 1/0 1/0 x x enable increment/decrement of the wcr pointed to by p 1 to p 0 x9241a
7 fn8164.7 august 17, 2015 scl from data output from transmitter 1 89 star t acknowledge master data output from receiver figure 7. acknowledge response from receiver x9241a
8 fn8164.7 august 17, 2015 detailed operation all four xdcp potentiometers s hare the serial interface and share a common architectu re. each potentiometer is comprised of a resistor array, a wiper counter register and four data registers. a detail ed discussion of the register organization and array operation follows. wiper counter register the x9241a contains four volat ile wiper counter registers (wcr), one for each xdcp potentiometer. the wcr can be envisioned as a 6-bit parallel and serial load counter with its outputs decoded to select one of sixty-four switches along its resistor array. the contents of the wcr can be altered in four ways: it may be written directly by the host via the write wcr instruction (serial load); i t may be written indirectly by transferring the c ontents of one of four associated data registers via the xf r data register instruction (parallel load); it can be modified one step at a time by the increment/decrement instruction; finally, it is loaded with the contents of its data regist er zero (dr0) upon power-up. the wcr is a volatile register; that is, its contents are lost when the x9241a is powered-down. although the register is automatically loaded with the value in dr0 upon power-up, it should be noted this may be different from the value present at power-down. data registers each potentiometer has four nonvolatile data registers. these can be read or written directly by the host and data can be transferred between any of the four data registers and the wcr. it should be no ted all operations changing data in one of these registers is a nonvolatil e operation and will take a maximum of 10ms. if the application does not r equire storage of multiple settings for the potentiometer, these registers can be used as regular memory locations that could possibly store system parameters or user preference data. serial data path from interface circuitry register 0 register 1 register 2 register 3 serial bus input parallel bus input wiper counter register inc/dec logic up/dn clk modified scl up/dn v h /r h if wcr = 00[h] then v w /r w = v l /r l if wcr = 3f[h] then v w /r w = v h /r h 8 6 c d e o u n t e r e c o d cascade dw cm control logic 2 v l /r l v w /r w figure 8. detailed potentiometer block diagram x9241a
9 fn8164.7 august 17, 2015 cascade mode the x9241a provides a mechanism for cascading the arrays. that is, the sixty-three resistor elements of one array may be cascaded (linked) with the resistor elements of an adjacent array. the v l /r l of the higher order array must be connected to the v h /r h of the lower order array (see figure 9). cascade control bits the data byte, for the three-byte commands, contains 6-bits (lsbs) for defining the wiper pos ition plus 2 high order bits, cm (cascade mode) and dw (disable wiper, normal operation). the state of the cm bit (bit 7 of wcr) enables or disables cascade mode. when the cm bit of the wcr is set to 0 the potentiometer is in the norm al operation mode. when the cm bit of the wcr is set to 1 the potentiometer is cascaded with its adjacent higher order potentiometer. for example; if bit 7 of wcr2 is set to 1, pot 2 will be cascaded to pot 3. the state of d w enables or disables the wiper. when the dw bit (bit 6 of the wcr) is se t to 0 the wiper is enabled; when set to 1 the wiper is disabled. if the wiper is disabled , the wiper terminal will be ele ctrically isolated and float. when operating in cascade mode v h /r h , v l /r l and the wiper terminals of the cascaded arrays must be electrically connected external ly. all but one of the wipers must be disabled. the user can alter t he wiper position by writing directly to the wcr or indirectly by transferring the contents of the data registers to the wcr or by using the increment/decrement command. when using the increment/de crement command the wiper position will automatically trans ition between arrays. the current position of the wiper can be determined by reading the wcr registers; if the dw bit is 0, the wiper in that arra y is active. if the current wiper position is to be maintained on power-down a global xfr wcr to data register command must be issued to store the po sition in nv memory before power-down. it is possible to connect three o r all four potentiometers in cascade mode. it is also possible to connect pot 3 to pot 0 as a cascade. the requirements for external connections of v l /r l , v h /r h and the wipers are th e same in these cases. v h0 /r h0 v l0 /r l0 v w0 /r w0 v l1 /r l1 v h1 /r h1 v w1 /r w1 v l2 /r l2 v h2 /r h2 v w2 /r w2 v l3 /r l3 v h3 /r h3 v w3 /r w3 pot 0 wcr0 pot 1 wcr1 pot 2 wcr2 pot 3 wcr3 external connection = figure 9. cascading arrays x9241a
10 fn8164.7 august 17, 2015 absolute maximum ratings thermal information supply voltage (v cc ) limits x9241a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v 10% max wiper current for 2k r total . . . . . . . . . . . . . . . . . . . . . . 4ma max wiper current for 10k and 50k r total . . . . . . . . . . . . . . 3ma voltage on sck, scl or any address input with respect to v ss . . . . . . . . . . . . . . . . . . . . . . . -1v to +7v voltage on any v h /r h , v w /r w or v l /r l referenced to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 v/-4v ? v = |v h /r h - v l /r l | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10v i w (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ma power rating (each pot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50mw temperature under bias. . . . . . . . . . . . . . . . . . . . . . . . -65 to +135c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions temperature (commercial) . . . . . . . . . . . . . . . . . . . . . 0c to +70c temperature (industrial). . . . . . . . . . . . . . . . . . . . . . .-40c to +85c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. analog specifications (over recommended operating conditi ons unless otherwise stated) . symbol parameter test condition limits unit min (note 11) typ max (note 11) r total end to end resistance -20 +20 % r w wiper resistance wiper current = (v h - v l )/r total 40 130 ? v term voltage on any v h /r h , v w /r w or v l /r l pin -3.0 +5 v noise ref: 1khz (note 7) ? 120 dbv resolution (note 7) 1.6 % absolute linearity (note 3) r w(n)(actual) - r w(n)(expected) 1 mi (note 5) relative linearity (note 4) r w(n + 1) - [r w(n) + mi ] 0.2 mi (note 5) temperature coefficient of r total (note 7) 300 ppm/c ratiometric temperature coefficient (note 7) 20 ppm/c c h /c l /c w potentiometer capacitances see circuit #3 and (note 7) 15/15/25 pf l al r h , r i , r w leakage current v in = v term . device is in stand-by mode. 0.1 1 a dc electrical specifications (over recommended operating conditions unless otherwise stated. ) symbol parameter test condition limits unit min (note 11) typ max (note 11) l cc supply current (active) f scl = 100khz, write/read to wcr, other inputs = v ss 3ma i sb v cc current (standby) scl = sda = v cc , addr. = v ss 200 500 a i li input leakage current v in = v ss to v cc 10 a i lo output leakage current v out = v ss to v cc 10 a v ih input high voltage 2 v v il input low voltage 0.8 v v ol output low voltage i ol = 3ma 0.4 v notes: 3. absolute linearity is utilized to determine actual wiper volt age versus expected voltage as det ermined by wiper position whe n used as a potentiometer. 4. relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. it is a measure of the error in step size. 5. mi = rtot/63 or (r h C r l )/63, single pot 6. max = all four arrays cascaded together, typical = individual array resolutions. x9241a
11 fn8164.7 august 17, 2015 power-up requirements (power up sequencing can affect c orrect recall of the wiper reg isters) the preferred powe r-on sequence is as follows: first v cc , then the potentiometer pins. it is suggested that vcc reach 9 0% of its final value before powe r is applied to the potentiometer pins. the v cc ramp rate specification shoul d be met, and any glitches or slope changes in the v cc line should be held to <1 00mv if possible. also, v cc should not reverse polar ity by more than 0.5v. notes: 7. limits should be considered ty pical and are not production te sted. 8. limits established by characte rization and are not production tested. 9. maximum wiper current is derated over temperature. see the wi per current derating curve. 10. t i value denotes the maximum noise glitch pulse width that the de vice will ignore on either scl o r sda pins. any noise glitch pu lse width that is greater than this maximum val ue will be considered as a vali d clock or data pulse and may cause communication failure to th e device. 11. parts are 100% tested at eit her +70c or +85c. over tempera ture limits established by characterization and are not product ion tested. symbol table endurance and data retention parameter min unit minimum endurance 100,000 data changes per bit per register data retention 100 years capacitance symbol parameter test condition typ unit c i/o (note 7) input/output capacitance (sda) v i/o = 0v 19 pf c in (note 7) input capacitance (a0, a1, a2, a3 and scl) v in = 0v 12 pf power-up timing symbol parameter min (note 11) typ max (note 11) unit t pur (note 8) power-up to initiation of read operation 1 ms t puw (note 8) power-up to initiation of write operation 5 ms t r v cc v cc power up ramp rate 0.2 50 v/ms ac conditions of test input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 input pulse levels v cc x 0.1 to v cc x 0.9 waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low dont care: changes allowed changing: state not known n/a center line is high impedance x9241a
12 fn8164.7 august 17, 2015 equivalent ac test circuit circuit #3 spice macro model guidelines for calculating typical values of bus pull-up resistors dcp wiper current de-rating curve 5v 1533 ? 100pf sda output r h c h 15pf c w r l c l r w r total 25pf 15pf macro model 120 100 80 40 60 20 20 40 60 80 100 120 0 0 bus capacitance (pf) min. resistance maximum resistance r max = c bus t r r min = i ol min v cc max =1.8k ? resistance (k ? ) 7 6 5 3 4 1 20 40 60 70 80 90 0 0 ambient temperature (c) maximum dcp wiper current 2 50 10 30 ac electrical specifications (over recommended operating conditions unless otherwise stated) . symbol parameter limits unit reference figure number(s) min (note 11) max (note 11) f scl scl clock frequency 0 100 khz 10 t low clock low period 4700 ns 10 t high clock high period 4000 ns 10 t r scl and sda rise time 1000 ns 10 t f scl and sda fall time 300 ns 10 t i , (note 11) noise suppression time constant (glitch filter) 20 ns 10 t su:sta start condition setup time (for a repeated start condition) 400 0 ns 10 and 12 t hd:sta start condition hold time 4000 ns 10 and 12 t high t su:sta t hd:sta t hd:dat t su:dat t low t f t su:sto t r t buf scl sda (data in) figure 10. input bus timing x9241a
13 fn8164.7 august 17, 2015 t su:dat data in setup time 250 ns 10 t hd:dat data in hold time 0 ns 10 t aa scl low to sda data out valid 3500 ns 11 t dh data out hold time 30 ns 11 t su:sto stop condition setup time 4000 ns 10 and 12 t buf bus free time prior to new transmission 4700 ns 10 t wr write cycle time (nonvolatile write operation) 10 ms 13 t stpwv wiper response time from stop generation 500 s 13 t clwv wiper response from scl low 1000 s 6 ac electrical specifications (over recommended operating conditions unless otherwise stated) . (continued) symbol parameter limits unit reference figure number(s) min (note 11) max (note 11) t aa t dh scl sda sda out (ack) sda out sda out figure 11. output bus timing t su:sto scl sda t hd:sta t su:sta stop condition start condition (data in) figure 12. start stop timing scl sda wiper output clock 8 sda in clock 9 ack stop t wr t stpwv start figure 13. write cycle and wiper response timing x9241a
14 fn8164.7 august 17, 2015 about intersil intersil corporation is a leading provider of innovative power management and precision analog solutions. the company's produc ts address some of the largest marke ts within the industrial and i nfrastructure, mobile computing and high-end consumer markets. for the most updated datasheet, application no tes, related documentation and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggesti ons for improving this datashe et by visiting www.intersil.com/ask . reliability reports are also a vailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes onl y and is believed to be accurate, but not warranted. please go to the web to make sure that you have the latest revision . date revision change august 17, 2015 fn8164.7 - ordering information table on page 2. - added revision history beginning with rev 1. - added about intersil verbiage. x9241a
15 fn8164.7 august 17, 2015 x9241a thin shrink small outline package family (tssop) n (n/2)+1 (n/2) top view a d 0.20 c 2x b a n/2 lead tips b e1 e 0.25 cab m 1 h pin #1 i.d. 0.05 e c 0.10 c n leads side view 0.10 cab m b c see detail x end view detail x a2 0 - 8 gauge plane 0.25 l a1 a l1 seating plane mdp0044 thin shrink small outline package family symbol millimeters tolerance 14 ld 16 ld 20 ld 24 ld 28 ld a 1.20 1.20 1.20 1.20 1.20 max a1 0.10 0.10 0.10 0.10 0.10 0.05 a2 0.90 0.90 0.90 0.90 0.90 0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 d 5.00 5.00 6.50 7.80 9.70 0.10 e 6.40 6.40 6.40 6.40 6.40 basic e1 4.40 4.40 4.40 4.40 4.40 0.10 e 0.65 0.65 0.65 0.65 0.65 basic l 0.60 0.60 0.60 0.60 0.60 0.15 l1 1.00 1.00 1.00 1.00 1.00 reference rev. f 2/07 notes: 1. dimension d does not include mold flash, protrusions or gat e burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. dimension e1 does not include interlead flash or protrusion s. interlead flash and protrusions shall not exceed 0.25mm per side. 3. dimensions d and e1 are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m - 1994.
16 fn8164.7 august 17, 2015 x9241a small outline package family (so) gauge plane a2 a1 l l1 detail x 4 4 seating plane e h b c 0.010 b m ca 0.004 c 0.010 b m ca b d (n/2) 1 e1 e n n (n/2)+1 a pin #1 i.d. mark h x 45 a see detail x c 0.010 mdp0027 small outline package family (so) symbol inches tolerance notes so-8 so-14 so16 (0.150) so16 (0.300) (sol-16) so20 (sol-20) so24 (sol-24) so28 (sol-28) a 0.068 0.068 0.068 0.104 0.104 0.104 0.104 max - a1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ? 0.003 - a2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ? 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ? 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ? 0.001 - d 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ? 0.004 1, 3 e 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ? 0.008 - e1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ? 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 basic - l 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ? 0.009 - l1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 reference - n 8 14 16 16 20 24 28 reference - rev. m 2/07 notes: 1. plastic or metal protrusions o f 0.006 maximum per side are n ot included. 2. plastic interlead protrusions of 0.010 maximum per side are not included. 3. dimensions d and e1 are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m - 1994
17 all intersil u.s. products are m anufactured, assembled and test ed utilizing iso9001 quality systems. intersil corporations quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products , see www.intersil.com fn8164.7 august 17, 2015 x9241a plastic dual-in-line packages (pdip) mdp0031 plastic dual-in-line package symbol inches tolerance notes pdip8 pdip14 pdip16 pdip18 pdip20 a 0.210 0.210 0.210 0.210 0.210 max a1 0.015 0.015 0.015 0.015 0.015 min a2 0.130 0.130 0.130 0.130 0.130 0.005 b 0.018 0.018 0.018 0.018 0.018 0.002 b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015 c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002 d 0.375 0.750 0.750 0.890 1.020 0.010 1 e 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010 e1 0.250 0.250 0.250 0.250 0.250 0.005 2 e 0.100 0.100 0.100 0.100 0.100 basic ea 0.300 0.300 0.300 0.300 0.300 basic eb 0.345 0.345 0.345 0.345 0.345 0.025 l 0.125 0.125 0.125 0.125 0.125 0.010 n 8 14 16 18 20 reference rev. c 2/07 notes: 1. plastic or metal protrusions o f 0.010 maximum per side are n ot included. 2. plastic interlead protrusions of 0.010 maximum per side are not included. 3. dimensions e and ea are measu red with the leads constrained p erpendicular to the seating plane. 4. dimension eb is measured wi th the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. d l a e b a1 note 5 a2 seating plane l n pin #1 index e1 12 n/2 b2 e eb ea c

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